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Principal RF/Analog IC Design Engineers

Description

Senior/Principal RF/Analog IC Design Engineer

We are working with a London based leading developer of high throughput, modular phased arrays whose unique innovation of electronically steerable antennas enable almost any vehicle surface to receive and send satellite signals.

Due to recent takeover and investment, several opportunities have arisen for Senior/Principal RF/Analog IC Design Engineers to complement the existing design team.

As a Principal RF Analogue IC Design Engineer you will be working on the specification, architecture design and circuit design of key circuits and sub-systems of integrated RF transceivers for next generation of satellite communications in various deep sub-micron technologies.

The salary for this role will be between £60,000 - £100,000 p/a dependant on experience

Technical Responsibilities:

  • Responsible for design of a complex transceiver blocks (currently in Ku band) in BiCMOS,22nM FDSOI process or other technologies.
  • Hands-on block-level and architecture-level design of various blocks such as LNA, Mixer, TIA, Filter, PA, Opamps, LO and Filters
  • Delivering highly competitive RF/Analog blocks with leading edge performance using innovative architectures and circuit implementations.
  • Work closely with the layout team on IP floor-planning, trial layout design, parasitic extraction and modifications.
  • Co-ordinate design activities with other colleagues and possible contractors.
  • Collaborate with CAD, process technology, package design and Antenna teams
  • Document own work and participate in design reviews
  • Provide broad technical expertise and mentor junior team members

Essential Skills:

  • An Engineering degree in a relevant discipline
  • Minimum of 5 years experience in RF, Analog and Mixed-Signal IC design (preferably up to 15GHz operating frequencies)
  • Excellent understanding of state-of-the-art RF CMOS circuit design and transceiver architectures
  • Experience of designing high performance RF circuits in deep sub-micron technology as well as a strong analytical approach with a clear track record of success and delivery
  • Advanced Cadence Virtuoso Design Framework Experience
  • Ability to work and interact with engineering teams across multiple disciplines during ASIC project stream development
  • Great communication skills and able to take responsibility for complex circuit and system designs and delivery to tight timescales
  • Experience on Layout design and strategy overview
  • Competitive salary
  • Modern open plan offices
  • Contributory pension
  • 25 days holiday (plus recognised public holidays) and holiday purchase scheme

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​St. Bartholomew's House,
Lewins Mead, Bristol,
BS1 2NH. United Kingdom

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London, England, London, EC2V, United Kingdom

  • Ad ID:  15139910
  • Ad Type:  Offered
  • Posted on:  02/08/2020, 03:02
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